Author/Speaker: Roseanne Duca, Applied Mechanics Engineer, STMicroelectronics
Title: Modeling of Thermo-Mechanical Stress Transmission from Packaging for Hall Sensors
Abstract: Sensors are nowadays integrated in all aspects of our lives. Whether to sense changes in the environment around us such as temperature, pressure or humidity levels or to measure dynamic movements such as acceleration or physical quantities such as magnetic fields all sensors are nowadays very well embedded in our daily lives. Various kinds of sensor technologies exist e.g. MEMS sensors, Optical Sensors and Hall sensors. When it comes to packaging of each of these sensors one common factor is that the decoupling of the sensing part of the device from the package housing is of outmost importance when designing a sensor package. Failure to do so can result in induced drifts in the sensor output.
Sensors used to sense a physical quantity, such as a Hall sensor sensing a magnetic field can be very sensitive to mechanical stresses. Normal mechanical stresses when high enough can lead to drift of the sensor’s output influencing its performance. Stresses coming from packaging such as epoxy molding compounds and other stress inducing processes can have a direct contribution to this drift. Understanding the stress contribution of each of these processes together with the mechanics of materials involved is of paramount importance in mitigating stresses that would eventually influence performance of sensor.
Author/Speaker: Zhan Yu, Associate VP, Marvell
Title: Industry’s First 3nm Data Infrastructure
Abstract: This paper demonstrates Marvell’s comprehensive silicon IP leadership for cloud, AI, networking, 5G, automotive, and custom solutions in 3nm foundry technology.
Marvell designed and validated the industry’s first 3nm IP test chip. This work proved the silicon design technology to handle the challenges in the industry’s most advanced technology node. The silicon validation results also proved Marvell’s advanced IP design capability in high-speed interconnect technology.
Author/Speaker: Lynn Wang, Principal Member of the Technical Staff, GlobalFoundries
Title: Advancing Design for Manufacturability (DFM) physical verification with machine learning
Abstract: Design for Manufacturability (DFM) physical verification methodologies, such as rule-based Manufacturability Aware Scoring (MAS) and pattern-based DRC+, have been developed to proactively aid design checking and fixing prior to semiconductor fabrication, enabling greater process margins and ease of manufacturability. First, an overview of state-of-the-art DFM detection methodologies for physical verification is presented. Then, silicon measurements are presented to showcase how complying with DFM methodologies deployed in the GlobalFoundries (GF) Process Design Kits (PDK) improves the manufacturability of layout designs. Next, these DFM detection methodologies are shown to integrate seamlessly with standard digital and custom/analog design flows. Lastly, industry’s first application of supervised machine learning to improve DFM physical verification targeting real errors more accurately for designers is presented.
Author/Speaker: Srividya Jayaram, Product Engineering Manager, Siemens EDA
Title: Using Predictive Design & Process Insights to Enable Smart Manufacturing in Semiconductor Fabs
Abstract: Modern semiconductor fabrication pushes the limits of chemistry and physics while simultaneously employing large-scale, cutting-edge processing techniques. While fab expansion and capital expenditures continue to grow, the human element has become ever more demanding and prone to error. To assist with this issue, computer-aided process engineering, process control, and tool monitoring will continue to rise in the coming years. This paper will present the details with results on using Calibre® Fab Insights tool to enable smart manufacturing in three major applications areas within the fab, that can ultimately help in accelerating the yield ramp. First area is process monitoring (PMON), where we leverage usage of design and process features to prescribe product dependent process adjustments which in turn help accelerate NPI , improve automated process control (APC), provide actionable insights to identify parameters that most impact any given process step. The second area is tool monitoring (TMON), where the ML model can help early detection of tool drifts, that cause tool to go out of control (OOC), by providing alerts to perform a predictive maintenance. This can reduce the process/tool tuning time to bring them back to spec after a preventive maintenance (PM) cycle. The final area of application highlighted is virtual cross metrology (CM) where a digital metrology twin is created that enables prediction of metrological measurements at every intermediate step along with wafer maps.
Author/Speaker: Rita J. Klein, Senior Manager-Diffusion/Metals NVM, Micron Technology
Title: 3D NAND vertical scaling – Structural and metallization challenges, related to word-line processing
Abstract: 3D architecture for NAND scaling has been adopted for several years. With it, additional tiers (silicon oxide/silicon nitride) can be stacked to further scale NAND memory, which enables a path to meet the demand for increased bit output while simultaneously cutting cost per bit in the future. A crucial step in 3D NAND manufacturing is the formation of the word lines (WLs). They are stacked vertically within the consecutive memory layers, connecting the memory cells. Scaling is done not only in the vertical direction but also in horizontal directions, which entails decreasing the memory hole pitch and increasing the number of memory holes in the block. The construction of WLs requires the exhumation of the tier stack nitride and backfill of the space with a metal. The above scaling vectors lead to a change in the WL’s aspect ratio (AR) and surface area both in the horizontal and vertical direction as well as changes in WL volume. Key processes impacted by these scaling challenges are wet process for the nitride exhume and metal deposition for the WL backfill. Wet process is experiencing an increase in tier stiction, a phenomenon which is driven by drying forces post wet etch of the nitride due to reduced vertical spacing of WLs. The reduced vertical pitch and the tier stiction / bending will lead to challenges for metal back fill by impacting the chemical pathways during the metal atomic layer deposition (ALD) process. Achieving a uniform and defect-free WL is crucial for consistent device performance.
Author/Speaker: Jinhong Yang, Sr. MTS, Qorvo
Title: Wafer-Based Approach to Improving and Monitoring Interconnect Reliability
Abstract: Qorvo®, a diversified market leader in RF and power, provides the industry’s broadest portfolio of critical enabling technologies with expertise in mobile devices, complex infrastructure and global aerospace and defense applications. Qorvo is committed to providing solutions that meet customers’ quality, reliability, and performance requirements, pursue excellence in the customer experience and continually drive improvement.
At Qorvo, a wafer-based reliability (WBR) methodology for evaluating process reliability enables timely process development. The same approach also allows for continuous monitoring of production processes over time.
The use of wafer-based reliability (WBR) methods to improve and monitor interconnect reliability are discussed in this paper. The experimental results indicate that BCB interconnect reliability is strongly impacted by via residue, via profile, seed metal coverage and plating voids. Chemical attack and galvanic corrosion could develop gradually without any warning and result in field failure.
Author/Speaker: Fan Chen, Assistant Professor, Indiana University
Title: System Support for Environmentally Sustainable Computing in Data Centers
Abstract: Modern data centers suffer from a deteriorating carbon foot-print due to the lack of system support for environmental sustainability. Although prior works create hardware accelerators and build renewable energy sources to enhance sustainability, it remains challenging to address the Quality of Service (QoS) degradation caused by renew-able energy supply and hardware recycling in both the computing and storage layers of system stacks: (1) prior accelerators suffer from large embodied and operational carbon footprints due to a lack of reconfigura-bility and an inability to make effective forward progress under renewable energy fluctuations; (2) it is difficult to employ recycled NAND flash chips in a data center due to their short lifetime, which significantly increases embodied energy consumption. This work presents our initial endeavor to address the deficiency in system support for environmentally sustain-able data centers. We propose to develop a reconfigurable hardware accelerator for intensive computing primitives used in data-intensive ap-plications. We develop a fractional NAND flash cell to prolong the lifetime of recycled flash chips and support graceful capacity degradation. We present our preliminary results, recognizing this as an ongoing initiative. We anticipate these contributions hold significant promise for advancing environmentally sustainable computing in data centers and will inspire further exploration in this critical research domain.
Author/Speaker: Rita Gupta, Fellow, AMD
Title: Shifting Paradigm of Memory System Architecture
Abstract: As systems today continue to scale to fuel the growth for cloud computing, AI/ML, the demands for memory capacity and memory bandwidth are ever increasing- across data centers, enterprise and HPC. The linear progression of memory system architecture relying on scaling of DDR speeds/channels cannot keep pace with the exponential growth of demand and increasing core count. Furthermore, another critical consideration in this context is managing the Total-Cost-of-Ownership (TCO) per performance with memory being a significant part in the system costs. To address these challenges, the paper discusses alternate system architecture options such as tiered memory architecture with heterogeneous compute.
The paper delves into various approaches to tiered memory and examines system performance data across one of the benchmarks and insights from the results. The paper also discusses how emerging technologies such as CXL are enabling heterogeneous memories with media agnostic, flexible and cost-effective solutions.
In conclusion, the paper advocates for a paradigm shift in system architecture, emphasizing the importance of developing memory solutions that incorporate a low-capacity high bandwidth tier and a capacity tier. By doing so, system architecture can better cope with the escalating demands of modern applications, ensuring improved performance, efficiency and TCO and enable usage models of future such as disaggregated and shared memory solutions.
Author/Speaker: Richa Mishara, Technical Lead / Hardware Analytics, Meta
Title: Hardware Evaluation with Telemetry Enablement for Grand Teton
Abstract: As AI models become increasingly sophisticated, the associated workloads become increasingly complex. Meta’s next-generation GPU-based hardware platform, Grand Teton presented novel challenges for infrastructure integration and telemetry enablement. The platform required a unique method of onboarding for telemetry and monitoring during test and validation phases. In this paper we discuss the need for monitoring readiness during early stages of hardware lifecycle. This involves actively monitoring hardware telemetry alongside synthetic workloads for both training and inference use cases. We describe Meta’s AI infrastructure requirements, examine the challenges encountered during hardware initialization, and explore the essential telemetry prerequisites. Within the paper, we will cover the steps we have taken to address these challenges. Firstly, we present a comprehensive monitoring readiness stack which covers system-level components to application-level metrics. Next, we will describe the telemetry enablement process, which aids in evaluating hardware for optimal performance. We will then showcase few case studies aimed at understanding usage patterns and characterizing the hardware during its early design and validation phases. We will also discuss scenarios for failure analysis during synthetic benchmark tests. We will be summarizing our efforts and the need for a standardized monitoring framework for future hardware platforms in large-scale datacenter environments.
Author/Speaker: Priyanka Bhatt, ASIC Digital Design Engineer, Synopsis
Title: Analog/Mixed-signal Fault Analysis Using Custom Fault Approach
Abstract: Recently, automotive chips are gaining significance due to their usage in Advanced Driver Assistance Systems (ADAS), vehicle connectivity systems, infotainment systems, etc. Due to the stringent safety & reliability requirements proposed with ISO 26262 standards, all the complex Soc’s need to adhere to them to meet their quality requirements. The rapid increase in mixed-signal designs across automotive chips should be ensured defect free as a primary goal. The faults in the design’s digital portion are detected largely based on well-established digital fault models and fault simulation techniques. However, targeting faults in the analog blocks through fault simulation is challenging and still in its nascent stages due to the vast number of possible values and non-discreet timing characteristics of analog signals. This paper defines an approach to evaluate the coverage of analog blocks in a design by performing analog fault simulation using the Custom Fault technique, which uses functional test vectors used in mixed-signal simulation to compare the circuit’s behavior under fault-free and faulty conditions.
Author/Speaker: Izzy Hossain, Senior Managing Engineer / Hardware Analytics, Intel
Title: FPGA End-to-end Security Validation: Comprehensive strategy to protect Intel FPGAs against malicious attack.
Abstract: This paper outlines a holistic approach to the end-to-end security validation of Intel FPGAs, designed to guarantee the efficacy of advanced security features such as Platform Attestation, Secure Boot, Secure Debug, Anti-Tamper, and Black Key Provisioning in safeguarding customers against potential threats. The rigorous validation process focuses on five pivotal categories. Category I focuses on verifying the functionality of crucial hardware components, to establish a secure foundation. Category II extends validation to cover both pre-silicon and post-silicon stages, ensuring seamless integration and intended functionality of FPGA elements. Category III combines a hackathon and negative test case assessments to unearth vulnerabilities and rectify potential security flaws. Category IV subjects the FPGA to extensive testing, assessing its resilience against a wide array of security threats, including side-channel attacks, fault injections, penetration testing, threat modeling, device attacks, remote attacks, and OEM attacks. Finally, Category V focuses on validating cryptographic algorithms and modules for compliance with NIST FIPS-140-3 certification standards, ensuring compliance with government system requirements and sensitive applications. This comprehensive approach underscores Intel’s unwavering commitment to security, strengthening its status as an industry leader in FPGA security assurance.
Author/Speaker: Ning Mi, Senior Principal Software Engineer, Cadence Design
Title: A Transaction-Based Customized DisplayPort Parallel Interface with Full Configurability
Abstract: The DisplayPort Verification IP(VIP) is instantiated by Users to validate their DisplayPort protocol RTL designs. Different RTL designs often require different specially designed parallel interfaces. These different interface requirements serve varying needs, such as speed-up of the simulation during unit testing; design under development with some blocks not yet ready; the DisplayPort design needs to be connected to other protocols; etc. It is time consuming to create a new physical pin interface for each of these different RTL designs. This paper provides the Transaction-Based Customized Interface, which is compatible with all user’s specific parallel interface requirements. This interface allows the user to use the VIP transactions and callback routines instead of predefined physical pins in their verification environment.