Artificial Intelligence (AI)
Accelerating FPGA Physical Design Closure through Generative AI
ARTEMIS: A Multi-Agent AI System for Automated Root-Cause Analysis and Optimization of RTL Verification Workflows
Keep Your Data, Share the Model: Federated Learning for Privacy-Preserving Hardware Anomaly Detection Across Distributed Fleets
Design Technology
Achieving Glitch Power Visibility via Delay-Shifted Analysis for Actionable Power Optimization
Constraint-Driven Routing Closure for High-Frequency Mixed-Signal Designs
Executable Interrupt Specifications: Managing Control-Plane Complexity in Disaggregated Server SoCs
Process/Packing/Assembly Technology
Mechanism-Driven Etch-Passivation Balance Engineering for LCDU Convergence Across Hybrid EUV Geometries
Split-Gate Inter-Poly Architecture for Electrical Gate Leakage and Mechanical Wafer Warpage Optimization in Trench FP-MOSFETs
System Technology
Making True Single-Stage EV Charging Practical: System-Level Redesign of a Dual-Active-Bridge On-Board Charger Enabled by Bidirectional GaN and Closed-Form Control
Trivializing Chip Reset Timing: A Novel Technique for SoC Backend Closure
Under the Hood of Hardware Systems for Accelerator-Aware Workloads: From Lab to Fleet
Test/Validation
Capping with Confidence: A Test & Validation Framework for Power Savings and a Lower Data-Center Carbon Footprint
On-Device Cryptographic Key Provisioning for PSA Level 3 MCU: Secure Firmware Synthesis and Attestation
Scaling Electro-Optical Test and Reliability Validation of Silicon Photonics for AI and Hyperscale Data Centers
