John Wuu is a Senior Fellow Design Engineer at AMD in Fort Collins, Colorado, specializing in memory technology and design, high performance cache design, and chiplet DTCO.  In addition to working across the company to define and deliver SRAM solutions, his recent contributions included the physical definition and technology co-development for AMD’s 3D V-Cache™.  Prior to joining AMD in 2006, he had been with Hewlett-Packard and then Intel, working on large L3 caches for Itanium processors.  He received his Bachelors and Masters degrees from MIT in 1997, and has served as a Technical Program Committee member for the VLSI Symposium since 2016, and for ISSCC since 2023.